The present invention relates to low power consumption technique for semiconductor integrated circuit and more specifically to the technique which may effectively be applied, for example, to an LSI (Large-Scale Integrated circuit) provided with a translation look-aside buffer memory used for virtual memory and an LSI including a processor core of the VLIW (Very Long Instruction Word) system.
In general, a processor which processes a large amount of data supports virtual memory. The virtual memory means the technique to show the limited address space for main memory as if it were provided with a vast address space in the main memory such as DRAM (Dynamic Random Access Memory) and the system including the secondary memory such as hard disk by providing a wide storage area for virtual memory in the secondary memory and allowing a processor to make access to the main memory by transferring a part of the data under the access request in this storage area to the main memory.
Since access is made from a processor using a virtual logical address in order to use virtual memory, this logical address must be converted to a physical address on the main memory. Moreover, since this address conversion has to be executed for each access to the virtual memory, a processor supporting the virtual memory is generally provided with a memory circuit called a translation look-aside buffer (TLB) which assures high speed address conversion for alleviation of overhead in the performance through the address conversion.
One of the processor architectures is called the VLIW system in which a plurality of execution circuits assuring parallel operations are provided to receive the instruction in which a plurality of instruction codes are combined and a plurality of execution circuits process in parallel a plurality of instruction codes. In the VLIW system processor architecture, the hardware is not required to judge possibility of simultaneous execution of each instruction code and the processor can obtain high throughput through the parallel processes only by sending, for the purpose of processing, a plurality of instruction codes included in one instruction to each execution circuit corresponding to the format thereof.
In this VLIW system, when the number of instruction codes to be executed simultaneously is comparatively small, it is require to attain the matching of instruction length by inserting the code of NOP (Non Operation) instruction which is not accompanied by effective processes. Moreover, the processors of VLIW system include the processor which compresses the instruction by adding instruction location information indicating the information of group boundary of instruction codes executed simultaneously and the format of each instruction code in place of eliminating the NOP instruction inserted to attain the matching of instruction length and then recovers this compressed instruction to the original instruction within the processor in order to execute the decoding process and execution process. With such compressed instruction, efficiency of instruction cache can be improved.
At present, power consumption of LSI is more increasing as the operation rate of LSI is improved and the integration density is enhanced. Moreover, since the LSI is often loaded to electronic devices which are driven with batteries such as portable phones and personal digital assistants (PDA), requirement for reduction in power consumption of LSI is more and more growing.
Accordingly, the inventors of the present invention have investigated reduction in power consumption of the translation look-aside buffer and processor of VLIW system described above.
As the prior art for realizing low power consumption of the translation look-aside buffer, the similar techniques have been disclosed respectively, for example, in the Japanese Patent Laid-Open Nos. Hei 11(1999)-134256, Hei 8(1996)-95864 and 2000-148589.
The technique of the Japanese Patent Laid-Open No. Hei 11(1999)-134256 realizes low power consumption by comparing the upper bits of the logical address with the preceding upper bits before the address conversion and then realizing the address conversion, when the upper bits are matched, using the preceding conversion result without execution of address conversion in the translation look-aside buffer.
In addition, the technique disclosed in the Japanese Patent Laid-Open No. Hei 8(1996)-95864 realizes low power consumption by comparing the upper bits (virtual page number) of logical address with the preceding upper bits before the address conversion and then setting, when the matching is attained, the translation look-aside buffer to non-active state using the preceding conversion result.
The technique disclosed in the Japanese Patent Laid-Open No. 2000-148589 realizes low power consumption by controlling the operation in such manner that only one translation look-aside buffer among those provided in a memory management unit is always operated.